We’ve developed a deep understanding of how the NI FlexRIO interfaces to high-end sub-systems to enable automated test & analysis, capitalizing on our knowledge bank of coding nuances and high-speed interface design.
Custom FlexRIO Adapter Module Development
Multifunction I/O on one custom built FAM – Analog In, Out and Digital IO custom
High-speed parallel/ Serial Data (100’s MHz)
Double Data Rate (DDR) I/O
LVDS I/O (single-ended, and LVDS or mLVDS)
High-speed Serial Data – 1Gbps+
Custom I/O interfacing
Custom connector interfacing to UUT (including High Density)
SFP+ connector interfacing
High-speed I/O Buffering
High-speed PCB Design with High Speed PCB Simulation for impedance matching and cross-talk considerations.
Power allotment planning
FlexRIO Application Development
CLiP development & modification – interface development & modification of NI standard FAMs CLiPS to allow for data delays, PLLs, etc.
VHDL & LabVIEW FPGA Development
Data to/from RAID
Custom low-level triggering (FPGA, RT)
Test sequencing to enable more complex testing and automation of tests
Algorithm development – filtering, thresholding, peak detection, FFT, interpolation, correlation, pulse measurements, etc.
Custom FlexRIO Adaptor Module supports HIL Test Upgrade
A custom-COTS approach reduces cost and delivery time.
Client – Major National Research Lab
Our client has a client (the end-user) for which they developed an HIL test system several years prior. Parts were obsolete and the system needed an upgrade. The prior system had many custom-designed electronic components which could not be replaced without a complete redesign.
Consequently, our client wanted to use COTS. However, one device needed 28 VDC digital I/O, a couple of lines which carried significant current (amp, not milliamp, levels) and at switching rates much higher than a COTS solid state relay could provide.
Viewpoint reviewed the requirements and created a hybrid COTS-custom solution. We combined an NI FlexRIO module with a custom FlexRIO Adapter Module (FAM) for the front end to satisfy the 28 VDC signals levels and required current drive.
COTS FlexRIO integrates into the remainder of our client’s PXI-based test system.
The Custom I/O was designed for flexibility. Our client can use this FAM for both their initial end-user and other programs / clients too.
Reduced cost relative to a completely custom solution.
Delivery time reduced by months relative to a custom solution
The custom FAM interfaced with the NI FlexRIO module, which offered low-level digital I/O (3.3 V logic), to digital signal conditioning hardware that provided the 28 VDC signal levels and required current drive.
Each I/O pin was configurable as input or output (source or sink). Each bank of 4 channels had an adjustable threshold level set via an adjustable DAC output. Some of the channels are designed for amp-level current drive, while the remainder were 250 mA. All I/O was fused appropriately.
Viewpoint also developed LabVIEW FPGA and VHDL to enable our client and the end-user to:
Configure the I/O as in or out.
Communicate to the DAC to allow custom input threshold trigger levels.
NI FlexRIO enables Device Evaluation & Characterization for high-data-rate sub-system
100s of man-hours saved in capturing the data.
Client – Automotive Manufacturer
New product development drove the need for validation of a new sub-system (a RADAR sensor ) for use in a next-gen system in an automobile. They needed a way to evaluate and characterize the performance of the component under various conditions that were not defined in the UUTs specs. They wanted to use as much COTS hardware as possible for this first run testing because of the expense of a custom test solution and the timeline.
The NI FlexRIO-based product validation system utilizes COTS hardware, along with some Viewpoint-developed custom software to allow for evaluation and characterization of the UUT.
The utilization of COTs (vs a custom-built FPGA board) test hardware.
100s of man-hours saved in capturing the data.
Allowed customer to manipulate captured data within the LabVIEW environment for more efficient testing, making changes on the fly.
Error Checking done at the FPGA Level allows for guaranteed valid transfers
Packet Decode completed at FPGA Level allows for real-time de-packetization for use in storing only payload data.
All Data captured with TDMS Files for use in over layering different scenarios.
Scalable to add additional serial data channels allowing for more than one sensor to be captured with a single FlexRIO card.
NI’s FlexRIO with NI’s LVDS FAM was used. The NI flying lead cable was utilized initially to connect to the UUT. On the software side custom VHDL was created to handle the 8b/10b serial stream data and clock recovery. The VHDL interfaced to LabVIEW FPGA which was utilized to stream the data to disk on the PXI-based system.
Custom FAM VHDL and LabVIEW FPGA interface Development
At maximum throughput, the systems needed to consume during record and produce during playback about 800 MB/s/slot.
Client: A large company involved in C4ISR
A large company involved in C4ISR was developing a system for a new high-speed digital sensor device. Viewpoint was contracted to build a test system used in design validation and ultimately endurance testing of the sensor. Since the sensor was a component of a larger system which was being developed at the same time, another test system was created to simulate the sensor by feeding signals into the system.
Both the amount of data and the frequencies of the various digital signals were nearly at the limit of hardware capabilities. At maximum throughput, the systems needed to consume during record and produce during playback about 800 MB/s/slot. The FPGA clock on the FlexRIO had to run up to 300 MHz. The skew between triggers for data transmission needed to be less than 5 ns even between multiple FlexRIO cards even when the parallel data paths has inherent skews associated with the sensor. Finally, the systems needed to handle clocks that might be out-of-phase.
Achieving these requirements required significant engineering design in the face of multiple possible roadblocks, any one of which could have eliminated a successful outcome.
Furthermore, as usual, the development timeline was tight. In this case, it was a very tight 3 months.
To meet the timeline, we had to work in parallel across several fronts:
LabVIEW-based application development for both record and playback
LabVIEW FPGA development for marshalling data between the controller and DRAM
Custom FAM circuit board design and build
FlexRIO FPGA CLIP nodes and code for low-level data handling
This sensor had several parallel data paths of clock and data lines with clock speeds up to 300 MHz on each path requiring exacting design and build of a custom FlexRIO Adapter Module (FAM) and unique custom CLIP nodes for extending the FlexRIO FPGA capabilities. The FAM also had a special connector for interfacing to the customer’s hardware.
Additional NI hardware and software completed the system components.
The host application, written in LabVIEW, managed the configuration of the data acquisition and the control of the LabVIEW RT-based FlexRIO systems. The configuration primarily dealt with the number of sensor channels in use, skew settings between digital lines, and other parameters that dealt with the organization of the data passed between the sensor and the FlexRIO.
Two FlexRIO applications were written, one for record and one for playback. Each FlexRIO application was written in LabVIEW, and managed the configuration of the FlexRIO cards and the movement of data between the FlexRIO cards and the RAID drives. Note that Windows supported for the RAID driver. Between 10 and 32 DMA channels were used for streaming, depending on the number of sensor channels being used.
And, each FlexRIO application had an FPGA layer, written in LabVIEW FPGA enhanced with custom CLIP nodes. For the record application, we developed a custom DRAM FIFO on the FPGA to assist with the latencies on the PXIe bus. For the playback application, we were able to stream directly from DRAM.
The FlexRIO and stock FAMs from NI were initially considered as candidates for this project. Clearly, working with commercial-off-the-shelf (COTS) components would be most effective. Three options were available at the project start which could accommodate the required clock frequencies, but none offered both the required channel counts and skew/routing limitations. Hence, we had to design a custom FAM. This decision, made before the start of the project, turned out to be wise in hindsight because the parallel development path resulted in some shifts of sensor requirements which could be accommodated with the custom FAM but might have led to a dead-end with a COTS FAM.
In LabVIEW FPGA, a CLIP Node is a method to import custom FPGA IP (i.e., code) into a LabVIEW FPGA application. CLIP stands for Component-Level Intellectual Property. We needed to use special Socketed CLIP Nodes (i.e., VHDL that can access FPGA pins) for this project because we could expose additional features of the Xilinx Virtex-5 not exposed in LabVIEW FPGA by accessing Xilinx primitives. Some specific features were:
Faster FPGA clocking
Additional clocking options
Individual clock and skew control
Custom PLL de-jitter nodes
Essentially, the FPGA design had a majority of FPGA code developed in LabVIEW FPGA and we used CLIP Nodes for interfacing the signals between the FlexRIO and the FAM.
FlexRIO Adapter Module
As mentioned earlier, we had to create a custom FAM because of the need to route high speed signals from customer-specific high density connectors while synchronizing signals across multiple data channels and FPGA modules to within one (300 MHz) clock cycle.
At these high-speeds, the FAM needed careful buffering and impedance matching both on the signals as well internal components on the FAM PCB. At the start of the design, we utilized Mentor Graphics HyperLynx High Speed DDR signaling Simulation software to minimize signal reflections prior to building actual hardware. This step saved countless hours in spinning physical hardware designs.
We designed the FAM to allow channel routing and access to additional clock and trigger pins on the Xilinx chip and PXIe backplane.
The choice to base these digital record and playback systems on NI hardware and software was critical to completing this project. The open architecture in both hardware (custom FAM) and software (CLIP Nodes) enabled us to include some very creative extensions to the base toolset without which the project would not have succeeded in the allotted pressured schedule and on a predetermined budget. We were able to stretch the capabilities of the hardware and software very close to their maximum specifications by combining COTS and custom much more cost effectively than a purely custom design.