Emulation of high-speed digital imaging subsystems
AEDIS
Reduce Time
Decreased time to deliver vs custom approach: ~2-6 months
Decrease Cost
Decreased cost vs custom approach: ~$200k-$500k
Flexibility & Future-proofing
Modular & COTS - enables quicker changeout of components (processors, chassis, interface hardware, RAID, software)
For validation and assessment
Parameter | Capability |
---|---|
Storage Capacity | 5+ TB |
Aggregate Capture Rate | 1+ GB/s |
AEDIS Features
AEDIS capabilities have dramatically increased over the past 10+ years. We keep up to date on new hardware technologies to follow the needs of our customers. Those years of maturity have honed AEDIS into a time-tested platform that handles the output (pitch) and/or input (catch) of images into digital imaging systems. The high-level features of the platform are:
- Image data stream conversion – bit and byte manipulation for SerDes, , byte endian structure, sequencing of pixels, rows, and frames.
- FPGA module(s) connect(s) to a fast backplane for data transfers to RAM, RAID, and CPU.
- COTs hardware modules to allow for much simpler DUT interfacing even with actual DUT cables. Modular code for customization of all functions such as FPGA-based I/O, command and response messaging, and bit stream handling.
- C# application with LabVIEW code for backbone FPGA and hardware interfaces.
- Send commands and receive status message handling.
- REST API service to integrate top-level test application to perform such functions as start/stop capture, start/stop generation, query system status (run, halt, errors), and perform loopback test.
- User-editable JSON configuration files for image definition and bit streams, including channel skew adjustments.
- User-editable JSON recipe file to control test flow for unique and repeatable test runs.
- RAID data storage for retrieval during generation and storage during capture.
- Hardware abstraction layer – handles interface translation for various hardware interfaces, including, but not limited to NI FlexRIO, NI HS Serial, NI DAQmx, and NI R Series cards.
- FPGA real-time processing, signal analysis, and signal generation with NI FlexRIO, including incorporation of proprietary VHDL into the FPGA.
Below is a simple example application screen using LabVIEW to interface to the AEDIS platform.
Figure 1 - Sample simple test application screen
AEDIS Signal Conditioning I/O Features
The AEDIS platform provides full functionality for baseline image pitch and image catch capabilities based on off-the-shelf PXIe hardware and AEDIS hardware connection (breakout ITA) interfaces.
Generally, your DUT’s signal I/O connects to the PXIe FPGA modules though buffer boards which connect directly to NI’s FlexRIO modules, generally PXIe-659x for SerDes/CML, PXIe-6569 for LVDS, and others as specifications dictate). These buffer boards mount into the AEDIS breakout ITA, providing quantity and type changes to accommodate the signal types used by the FPA and associated electronics.
- High-speed FPA/ROIC and FPA electronics data path using LVDS and/or SerDes.
- DUT Command interface support.
- Clock and data command control driven by FPGAs.
- SPI command / response message control.
- FPGA I/O signals are buffered and buffer boards contain test points for probing and timing calibration.
- Signal conditioning boards provide:
- Power monitoring and DUT protection via an onboard µC.
- Each channel buffer provides equalization and pre/de-emphasis with the setup controlled by a µC in communication with the AEDIS application.
- LVDS rates up to 1.25 Gbps with up to 32 input and 32 output channels per module.
- Per line programable transmit pre-emphasis and receive equalization.
- CML has per line programable transmit pre-emphasis and receive equalization buffering with AC-coupled pairs with signaling rates to 6.25 Gbps per pair have been used with up to 4 input and 4 output channels per module.
- Per line programable input equalization, output de-emphasis, differential voltage and slew rate limiting.
- High-speed SEARAY™ connection to personality module.
- Mates with NI FlexRIO PXIe-659x modules for SerDes/CML and PXIe-6569 for LVDS.
- External synchronization.
The image below shows the AEDIS CML SerDes “FIM02” module. Test probes can be placed on this module to test signal integrity and timing.
Figure 2 - CML SerDes buffer I/O module
The image below the AEDIS LVDS “FIM03” module. Using the same connectors as CML SerDes module. Test probes can be placed on pads exposed on this module.
Figure 3 – LVDS buffer I/O module
AEDIS Breakout ITA Features
The AEDIS breakout ITA chassis is designed to hold up to 4 buffer boards along with a built-in power board to power the I/O buffer modules. The I/O module mix is configurable. The buffer I/O modules are connected to the high-speed ITA connectors via a PCB which provides the conversions to your DUT’s connectors and cables.
Other I/O schemes needing different channel types and counts and, especially, specific user connector types and counts, rely on the customizability of the PCB to make the connections. Often, the user wants a custom PCB so actual product (DUT) cables and connectors can directly connect to the AEDIS hardware.
The image below shows a breakout with 16 SERDES pairs, 32 LVDS Inputs and outputs. Shown with two Airborne VerSI connectors.
Figure 4 - AEDIS breakout ITA (top and back panels removed for clarity)
Benefits
For many people, the AEDIS platform offers a complete design validation and manufacturing test system for designing and manufacturing the FPAs and associated electronics in their EO/IR imaging products. Customization is available for those that have unique needs.
AEDIS offers these high-level benefits and more:
- Reduced schedule time and development cost
- Core set of software components ready to use.
- REST API to interface AEDIS to your test set
- Pre-built buffer electronics and ITA work with NI FlexRIO hardware.
- JSON file defines sensor size, interfaces, and IO count.
- Unique recipe JSON file for controlling test flow.
- Validation readiness
- AEDIS pitch platforms can be validated by AEDIS catch platform and vice versa.
- Loopback capable
- I/O buffer hardware has test points to validate signal integrity and correctness.
- Customization
- Single PCB for configuring your specific interconnects and channel counts.
- Extendable and modular hardware and software architecture.
- JSON-based script to execute your specific test types.
We’ve found that AEDIS typically starts at about 80% complete for each customer system, since each customer brings unique needs related to the digital data channel connection schemes and combinations of data and clock details. Those unique needs usually require building configuration files and/or software customization that consumes less than 20% of the overall scope of the test system.